The 93K’s TPP architecture allows independent timing and level per pin. The manual details:
Tip from the manual: Always initialize
setLevels()beforesetTimings()in your test method, else you risk undefined pin states.
Example from the manual (simplified):
#include <testmethod.h>
void MyDC_Test::execute()
FORCE_PIN(VDD, 3.3, 100e-3); // Force 3.3V at 100mA
MEASURE_PIN(VIO, 0, 1e-6); // Measure leakage
TEST(measured_io < 500e-9, "Leakage high");
The manual specifies all available FORCE_PIN, MEASURE_PIN, FETCH_TIMING() macros.
Important: Do not trust random PDF websites. They often host obsolete versions (e.g., Verigy V4.x instead of Advantest V8.x). verigy 93k tester manual
Pro Tip: Never use a third-party or scanned PDF. Always download the official manual for your exact firmware version from Advantest’s customer portal (V93000 Knowledge Base).
Searching a static PDF is slow. Build a living Verigy 93K tester manual strategy: The 93K’s TPP architecture allows independent timing and
The 93K is a modular, scalable tester. A manual for a base configuration (e.g., 128 digital channels, 4 PS1600 power supplies) looks vastly different from a system with 1024 channels, RF modules, and high-speed optical I/O.
While Advantest acquired Verigy in 2011, the legacy of the Verigy 93K remains deeply embedded in the hardware and software vernacular. Most existing literature, user forums, and internal company knowledge bases still refer to the Verigy 93K tester manual because the foundational architecture—the Tester Per Pin (TPP) architecture—was solidified under Verigy. Tip from the manual : Always initialize setLevels()
Searching for "Verigy 93K tester manual" yields more precise, older, and sometimes more hardware-focused documents than searching for "Advantest 93K." Recognizing this nuance is key to efficient troubleshooting.
The 93K uses burst tables to sequence patterns. The manual explains: