read_file -format verilog [list $my_design.v memory_controller.v] current_design $my_design link
report_timing > ./reports/timing.rpt
For further learning, consult the dc_ug.pdf (User Guide) from the 2021 documentation suite, specifically Chapters 6 (Constraints) and 11 (Compile Strategies). synopsys design compiler tutorial 2021
Good luck with your synthesis!
set_load 0.05 [all_outputs]
Create a .synopsys_dc.setup in your run directory:
# Library paths – 2021 format uses search_path set search_path [list . ../rtl ../libs $SYNOPSYS_DC_HOME/libraries/syn]
exit
You must describe the external environment. If data comes from another block, how long does it take to arrive relative to the clock? read_file -format verilog [list $my_design
# Assume the input signal comes from a block with max delay of 3ns
set_input_delay -max 3 -clock clk [get_ports data_in]
# Assume the output signal must be ready 2ns before the next clock edge
set_output_delay -max 2 -clock clk [get_ports data_out]
After elaboration, you must resolve references and check the design structure.
# Link resolves all instance references to library cells
link
# Check design for issues (e.g., unresolved references, floating ports)
check_design